Non-volatile memory chips are used in a wide variety of electrical applications, computers, communications devices, consumer electronics, and any other application where data must be retained when power is no longer being supplied. Flash erasable programmable read-only memory (EPROM) chips are non-volatile memory chips which also offer the ability of being programmed and erased. In order to program and erase these flash EPROM chips, high voltages varying from 10 to 16 volts are typically required to perform the programming and erasing operations. These high voltages are commonly referred to as Vpp. The high voltages are usually generated on the flash EPROM chips based on an externally supplied low voltage power suppy (Vcc). Circuitry, such as “charge pumps,” on the flash EPROM chip take the Vcc power supply voltage and outputs the requisite higher Vpp voltage. The charge pumps are basically voltage multiplication circuits, and the techniques for their construction are well known to those skilled in the non-volatile memory arts.
It is oftentimes desirable to control the rise times (e.g., ramp rate) of the on-chip generated high voltages (i.e., Vpp) for flash EPROMs. This is due to the fact that if the rise time of Vpp were too fast, it may impose undue stress on the flash EPROM memory core cells when the Vpp is applied to the control gate of the cell during channel hot electron programming or programming via Fowler-Nordheim tunneling.
Therefore, there exists a need for a circuit or method which is capable of accurately control the rise time of an on-chip generated high voltage or Vpp. The present invention offers a unique, novel solution which is especially relevant to Flash EPROM and other non-volatile memories which require high voltages for their program and/or erase procedures.